Electrical Engineering researchers build and demonstrate a compact, programmable graphics processor on an FPGA board, aiming to power affordable devices like e-rickshaw dashboards, navigation terminals and educational e-readers.
Researchers at IIT Delhi have developed what the institute is calling India's first working, demonstrable micro-GPU designed entirely indigenously by a university team. The technology, created by the institute's Electrical Engineering Department, has been successfully demonstrated on a standard field-programmable gate array (FPGA) development board.
The project was led by MTech students Nammi Akash and M Ravi Teja, under the guidance of Professor Jayadeva and Professor Kaushik Saha. The development holds particular significance because graphics processing units, essential components for handling images, visuals and display functions in electronic devices, are currently largely imported for use in Indian hardware systems.
A compact alternative to conventional GPUs
Unlike the large, high-performance GPUs found in advanced computing systems and gaming machines, the IIT Delhi team's micro-GPU is a smaller, programmable variant built specifically for devices requiring basic graphics and display capabilities. The researchers demonstrated its functionality by successfully rendering graphics on a Spartan-7 FPGA board.
Professor Jayadeva said the project underscores the educational and research value of programmable graphics hardware in developing computing platforms that are both affordable and socially relevant, noting that several technical innovations were necessary to get the design working on standard FPGA hardware.
According to the researchers, the design has been structured so it can eventually be deployed either on programmable hardware platforms like FPGAs or integrated directly into a dedicated chip. The team envisions applications in areas such as industrial display systems, simple human-machine interfaces, dashboard navigation systems for e-rickshaws, navigation terminals for small fishing vessels, and educational e-book readers — positioning the technology for everyday and specialised use cases rather than high-performance computing.
Professor Kaushik Saha said the initiative gives students an opportunity to integrate concepts spanning arithmetic hardware, programmable architectures, compiler design and embedded systems within a single project, while also tackling broader questions around accessible computing.
Next steps: scaling up and exploring chip production
Looking ahead, the research team is now working on developing a larger graphics processor architecture featuring between 8 and 16 cores, alongside plans to build an optimised compiler and supporting software tools for the system.
The researchers are additionally exploring a proof-of-concept built on a 65-nanometre chip fabrication process, with plans to pursue funding for chip development, system integration, and eventual commercial deployment.
Describing their goal, Akash and Ravi Teja said their aim was to build a compact yet genuinely programmable graphics-processing architecture suitable for implementation on FPGAs, with future potential for realisation as an application-specific integrated circuit (ASIC).
